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| author | Andrea Fioraldi <andreafioraldi@gmail.com> | 2019-07-20 14:23:07 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-07-20 14:23:07 +0200 |
| commit | 914426d8877a111563dca3d4ec769c9ee95254e6 (patch) | |
| tree | 646b71fafb67d6f1c8ccdad648c45e9a1dd1ad53 /qemu_mode/patches/i386-translate.diff | |
| parent | 302e71779095357d1f04e97085a6db9dd10530ae (diff) | |
| parent | 27928fbc946c4bed18534c565354cefef8eca04a (diff) | |
| download | afl++-914426d8877a111563dca3d4ec769c9ee95254e6.tar.gz | |
Merge pull request #26 from vanhauser-thc/qemu-compcov
Qemu CompCov
Diffstat (limited to 'qemu_mode/patches/i386-translate.diff')
| -rw-r--r-- | qemu_mode/patches/i386-translate.diff | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/qemu_mode/patches/i386-translate.diff b/qemu_mode/patches/i386-translate.diff new file mode 100644 index 00000000..0bc48828 --- /dev/null +++ b/qemu_mode/patches/i386-translate.diff @@ -0,0 +1,33 @@ +diff --git a/target/i386/translate.c b/target/i386/translate.c +index 0dd5fbe4..b95d341e 100644 +--- a/target/i386/translate.c ++++ b/target/i386/translate.c +@@ -32,6 +32,8 @@ + #include "trace-tcg.h" + #include "exec/log.h" + ++#include "../patches/afl-qemu-cpu-translate-inl.h" ++ + #define PREFIX_REPZ 0x01 + #define PREFIX_REPNZ 0x02 + #define PREFIX_LOCK 0x04 +@@ -1343,9 +1345,11 @@ static void gen_op(DisasContext *s1, int op, TCGMemOp ot, int d) + tcg_gen_atomic_fetch_add_tl(s1->cc_srcT, s1->A0, s1->T0, + s1->mem_index, ot | MO_LE); + tcg_gen_sub_tl(s1->T0, s1->cc_srcT, s1->T1); ++ afl_gen_compcov(s1->pc, s1->cc_srcT, s1->T1, ot); + } else { + tcg_gen_mov_tl(s1->cc_srcT, s1->T0); + tcg_gen_sub_tl(s1->T0, s1->T0, s1->T1); ++ afl_gen_compcov(s1->pc, s1->T0, s1->T1, ot); + gen_op_st_rm_T0_A0(s1, ot, d); + } + gen_op_update2_cc(s1); +@@ -1389,6 +1393,7 @@ static void gen_op(DisasContext *s1, int op, TCGMemOp ot, int d) + tcg_gen_mov_tl(cpu_cc_src, s1->T1); + tcg_gen_mov_tl(s1->cc_srcT, s1->T0); + tcg_gen_sub_tl(cpu_cc_dst, s1->T0, s1->T1); ++ afl_gen_compcov(s1->pc, s1->T0, s1->T1, ot); + set_cc_op(s1, CC_OP_SUBB + ot); + break; + } |