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| author | Tobias Geerinckx-Rice <me@tobias.gr> | 2019-08-26 15:28:44 +0200 |
|---|---|---|
| committer | Tobias Geerinckx-Rice <me@tobias.gr> | 2019-08-26 15:56:32 +0200 |
| commit | f27cb0f1dd5ba445e9fef982b0e8554c0af84aee (patch) | |
| tree | 7f2af080a1da038491a0c0b1b91e0db086ae5eb8 | |
| parent | 24b03073e5351bfb0fc466550d48dedd60022aeb (diff) | |
| download | guix-f27cb0f1dd5ba445e9fef982b0e8554c0af84aee.tar.gz | |
gnu: iverilog: Update to 10.3.
* gnu/packages/fpga.scm (iverilog): Update to 10.3.
| -rw-r--r-- | gnu/packages/fpga.scm | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/gnu/packages/fpga.scm b/gnu/packages/fpga.scm index 7b661d39ac..b4f259bf3a 100644 --- a/gnu/packages/fpga.scm +++ b/gnu/packages/fpga.scm @@ -85,20 +85,20 @@ formal verification.") (define-public iverilog (package (name "iverilog") - (version "10.2") + (version "10.3") (source (origin (method url-fetch) (uri (string-append "ftp://ftp.icarus.com/pub/eda/verilog/v10/" "verilog-" version ".tar.gz")) (sha256 - (base32 - "0075x5nsxwkrgn7b3635il9kw7mslckaji518pdmwdrdn7fxppln")))) + (base32 + "1vv88ckvfwq7mrysyjnilsrcrzm9d173kp9w5ivwh6rdw7klbgc6")))) (build-system gnu-build-system) (native-inputs `(("flex" ,flex) ("bison" ,bison) - ("ghostscript" ,ghostscript))) ; ps2pdf + ("ghostscript" ,ghostscript))) ; ps2pdf (home-page "http://iverilog.icarus.com/") (synopsis "FPGA Verilog simulation and synthesis tool") (description "Icarus Verilog is a Verilog simulation and synthesis tool. |