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| author | Cayetano Santos <csantosb@inventati.org> | 2024-10-16 12:19:11 +0200 |
|---|---|---|
| committer | Zheng Junjie <zhengjunjie@iscas.ac.cn> | 2024-10-20 20:05:39 +0800 |
| commit | b32f8bc9da74158330cebdbcb481d41e1be6d1ce (patch) | |
| tree | 57c7024ac37b5cf31425587f0b0ef02c6c4d471c /gnu/packages/fpga.scm | |
| parent | cf33081e182b6589d9589c2d0c2ac131ff712253 (diff) | |
| download | guix-b32f8bc9da74158330cebdbcb481d41e1be6d1ce.tar.gz | |
gnu: iverilog: Update to 12.0.
* gnu/packages/fpga.scm (iverilog): Update to 12.0. [source]: Switch to git-fetch. [arguments]: Use G-expressions. Set #:bootstrap-scripts to #~(list "autoconf.sh"). Set #:test-target to "check". [home-page]: Update to new home page. [native-inputs]: Add autoconf, gperf, remove ghostscript and zlib. Change-Id: I55c3142aa41b190fef79572576cac6fc02473645
Diffstat (limited to 'gnu/packages/fpga.scm')
| -rw-r--r-- | gnu/packages/fpga.scm | 34 |
1 files changed, 20 insertions, 14 deletions
diff --git a/gnu/packages/fpga.scm b/gnu/packages/fpga.scm index ea81054d5b..545ec3482d 100644 --- a/gnu/packages/fpga.scm +++ b/gnu/packages/fpga.scm @@ -107,23 +107,29 @@ formal verification.") (define-public iverilog (package (name "iverilog") - (version "11.0") - (source (origin - (method url-fetch) - (uri - (string-append "ftp://ftp.icarus.com/pub/eda/verilog/v11/" - "verilog-" version ".tar.gz")) - (sha256 - (base32 - "1mamlrkpb2gb00g7xdddaknrvwi4jr4ng6cfjhwngzk3ddhqaiym")))) + (version "12.0") + (source + (origin + (method git-fetch) + (uri (git-reference + (url "https://github.com/steveicarus/iverilog") + (commit + (string-append "v" (string-replace-substring version "." "_"))))) + (file-name (git-file-name name version)) + (sha256 + (base32 "1cm3ksxyyp8ihs0as5c2nk3a0y2db8dmrrw0f9an3sl255smxn17")))) (build-system gnu-build-system) (arguments - `(#:make-flags (list (string-append "CC=" ,(cc-for-target))))) - (native-inputs - (list flex bison ghostscript zlib)) ; ps2pdf - (home-page "http://iverilog.icarus.com/") + (list + #:test-target "check" + #:make-flags #~(list (string-append "PREFIX=" + #$output)) + #:bootstrap-scripts #~(list "autoconf.sh"))) + (native-inputs (list autoconf bison flex gperf)) + (home-page "https://steveicarus.github.io/iverilog") (synopsis "FPGA Verilog simulation and synthesis tool") - (description "Icarus Verilog is a Verilog simulation and synthesis tool. + (description + "Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a compiler, compiling source code written in Verilog (IEEE-1364) into some target format. For batch simulation, the compiler can generate an intermediate form |