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authorAndrew Miloradovsky <andrew@interpretmath.pw>2021-01-24 08:07:40 +0000
committerNicolas Goaziou <mail@nicolasgoaziou.fr>2021-01-28 14:34:33 +0100
commitfc4834f83ba825d31d22fc548b7d99c1bd033601 (patch)
tree82e96d484ce2c12d009d7fd6d276bbb4bd32511c /gnu/packages/fpga.scm
parent049e06b603ef0b8fcf5fa314379b9c525c58f53f (diff)
downloadguix-fc4834f83ba825d31d22fc548b7d99c1bd033601.tar.gz
gnu: Add systemc.
* gnu/packages/fpga.scm (systemc): New variable.

Signed-off-by: Nicolas Goaziou <mail@nicolasgoaziou.fr>
Diffstat (limited to 'gnu/packages/fpga.scm')
-rw-r--r--gnu/packages/fpga.scm30
1 files changed, 30 insertions, 0 deletions
diff --git a/gnu/packages/fpga.scm b/gnu/packages/fpga.scm
index 96ba0026f9..9b3e8acb12 100644
--- a/gnu/packages/fpga.scm
+++ b/gnu/packages/fpga.scm
@@ -467,3 +467,33 @@ a hardware description and verification language. ")
     (description "This package provides a VHDL compiler and simulator.")
     (home-page "https://github.com/nickg/nvc")
     (license license:gpl3+)))
+
+(define-public systemc
+  (package
+    (name "systemc")
+    (version "2.3.3")
+    (source
+     (origin
+       (method url-fetch)
+       (uri (string-append
+             "https://accellera.org/images/downloads/standards/"
+             "systemc/systemc-" version ".tar.gz"))
+       (sha256
+        (base32 "0gvv3xmhiwx1izmzy06yslzqzh6ygrgmw53xqfmyvbz5a6ivk0ap"))))
+    (native-inputs `(("perl" ,perl)))
+    (build-system gnu-build-system)
+    (arguments '(#:configure-flags '("--enable-debug")))
+    (home-page "https://accellera.org/community/systemc")
+    (synopsis "Library for event-driven simulation")
+    (description
+     "SystemC is a C++ library for modeling concurrent systems, and the
+reference implementation of IEEE 1666-2011.  It provides a notion of timing as
+well as an event-driven simulations environment.  Due to its concurrent and
+sequential nature, SystemC allows the description and integration of complex
+hardware and software components.  To some extent, SystemC can be seen as
+a Hardware Description Language.  However, unlike VHDL or Verilog, SystemC
+provides sophisticated mechanisms that offer high abstraction levels on
+components interfaces.  This, in turn, facilitates the integration of systems
+using different abstraction levels.")
+    ;; homepages.cae.wisc.edu/~ece734/SystemC/Esperan_SystemC_tutorial.pdf
+    (license license:asl2.0)))