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| author | Marius Bakke <mbakke@fastmail.com> | 2018-02-20 17:36:56 +0100 |
|---|---|---|
| committer | Marius Bakke <mbakke@fastmail.com> | 2018-02-20 17:36:56 +0100 |
| commit | 7f69459aca16756f35f08049c64a1bd77d23f33e (patch) | |
| tree | 1d267fb62feab89de5d97582672540cbaa37392c /gnu/packages/fpga.scm | |
| parent | 4a82722a658220ec1e10f9f2d5d77407d38db90e (diff) | |
| parent | b1989c12501e880afab62d3ff961791906fef350 (diff) | |
| download | guix-7f69459aca16756f35f08049c64a1bd77d23f33e.tar.gz | |
Merge branch 'master' into staging
Diffstat (limited to 'gnu/packages/fpga.scm')
| -rw-r--r-- | gnu/packages/fpga.scm | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/gnu/packages/fpga.scm b/gnu/packages/fpga.scm index f3dc805e36..60c5f96a87 100644 --- a/gnu/packages/fpga.scm +++ b/gnu/packages/fpga.scm @@ -1,6 +1,7 @@ ;;; GNU Guix --- Functional package management for GNU ;;; Copyright © 2016 Danny Milosavljevic <dannym@scratchpost.org> ;;; Copyright © 2016, 2017 Theodoros Foradis <theodoros@foradis.org> +;;; Copyright © 2018 Tobias Geerinckx-Rice <me@tobias.gr> ;;; ;;; This file is part of GNU Guix. ;;; @@ -83,7 +84,7 @@ formal verification.") (define-public iverilog (package (name "iverilog") - (version "10.1.1") + (version "10.2") (source (origin (method url-fetch) (uri @@ -91,7 +92,7 @@ formal verification.") "verilog-" version ".tar.gz")) (sha256 (base32 - "1nnassxvq30rnn0r2p85rkb2zwxk97p109y13x3vr365wzgpbapx")))) + "0075x5nsxwkrgn7b3635il9kw7mslckaji518pdmwdrdn7fxppln")))) (build-system gnu-build-system) (native-inputs `(("flex" ,flex) @@ -104,7 +105,7 @@ It operates as a compiler, compiling source code written in Verilog (IEEE-1364) into some target format. For batch simulation, the compiler can generate an intermediate form called vvp assembly. -This intermediate form is executed by the ``vvp'' command. +This intermediate form is executed by @command{vvp}. For synthesis, the compiler generates netlists in the desired format.") ;; GPL2 only because of: ;; - ./driver/iverilog.man.in |