diff options
author | Maxim Cournoyer <maxim.cournoyer@gmail.com> | 2021-12-13 16:29:21 -0500 |
---|---|---|
committer | Maxim Cournoyer <maxim.cournoyer@gmail.com> | 2021-12-13 16:29:21 -0500 |
commit | 6dffced09ecda024e0884e352778c221ad066fd6 (patch) | |
tree | 1707e8d8df4d9c47317a39ab6abbfc2ca66a6c29 /gnu/packages/fpga.scm | |
parent | b603554ed044638dd40b6863d5dada59eefe03b8 (diff) | |
parent | e3196755e60ba7f1ed9d432e73f26a85e0c8893c (diff) | |
download | guix-6dffced09ecda024e0884e352778c221ad066fd6.tar.gz |
Merge branch 'core-updates-frozen' into 'master'.
At last!
Diffstat (limited to 'gnu/packages/fpga.scm')
-rw-r--r-- | gnu/packages/fpga.scm | 82 |
1 files changed, 39 insertions, 43 deletions
diff --git a/gnu/packages/fpga.scm b/gnu/packages/fpga.scm index 661ba41793..13970e949a 100644 --- a/gnu/packages/fpga.scm +++ b/gnu/packages/fpga.scm @@ -74,9 +74,9 @@ "1syygi1x40rdryih3galr4q8yg1w5bvdzl75hd27v1xq0l5bz3d0")))) (build-system gnu-build-system) (native-inputs - `(("unzip" ,unzip))) + (list unzip)) (inputs - `(("readline" ,readline))) + (list readline)) (arguments `(#:tests? #f ; no check target #:phases @@ -108,9 +108,7 @@ formal verification.") "1vv88ckvfwq7mrysyjnilsrcrzm9d173kp9w5ivwh6rdw7klbgc6")))) (build-system gnu-build-system) (native-inputs - `(("flex" ,flex) - ("bison" ,bison) - ("ghostscript" ,ghostscript))) ; ps2pdf + (list flex bison ghostscript)) ; ps2pdf (home-page "http://iverilog.icarus.com/") (synopsis "FPGA Verilog simulation and synthesis tool") (description "Icarus Verilog is a Verilog simulation and synthesis tool. @@ -201,23 +199,23 @@ For synthesis, the compiler generates netlists in the desired format.") iverilog "\""))) #t)))))) (native-inputs - `(("pkg-config" ,pkg-config) - ("python" ,python) - ("bison" ,bison) - ("flex" ,flex) - ("gawk" , gawk) ; for the tests and "make" progress pretty-printing - ("tcl" ,tcl) ; tclsh for the tests - ("iverilog" ,iverilog))) ; for the tests + (list pkg-config + python + bison + flex + gawk ; for the tests and "make" progress pretty-printing + tcl ; tclsh for the tests + iverilog)) ; for the tests (inputs - `(("tcl" ,tcl) - ("readline" ,readline) - ("libffi" ,libffi) - ("graphviz" ,graphviz) - ("psmisc" ,psmisc) - ("xdot" ,xdot) - ("abc" ,abc))) + (list tcl + readline + libffi + graphviz + psmisc + xdot + abc)) (propagated-inputs - `(("z3" ,z3))) ; should be in path for yosys-smtbmc + (list z3)) ; should be in path for yosys-smtbmc (home-page "http://www.clifford.at/yosys/") (synopsis "FPGA Verilog RTL synthesizer") (description "Yosys synthesizes Verilog-2005.") @@ -258,7 +256,7 @@ For synthesis, the compiler generates netlists in the desired format.") #t)) (delete 'configure)))) (inputs - `(("libftdi" ,libftdi))) + (list libftdi)) (native-inputs `(("python-3" ,python) ("pkg-config" ,pkg-config))) @@ -285,12 +283,12 @@ Includes the actual FTDI connector.") (base32 "1fmxsywgs45g88ra7ips5s2niiiwrkyxdcy742ws18dfk2y4vi9c")))) (inputs - `(("boost" ,boost) - ("eigen" ,eigen) - ("icestorm" ,icestorm) - ("python" ,python) - ("qtbase" ,qtbase-5) - ("yosys" ,yosys))) + (list boost + eigen + icestorm + python + qtbase-5 + yosys)) (build-system cmake-build-system) (arguments `(#:configure-flags `("-DARCH=ice40" @@ -335,7 +333,7 @@ FOSS FPGA place and route tool.") (("#!/usr/bin/python") "#!/usr/bin/python2")) #t))))) (inputs - `(("icestorm" ,icestorm))) + (list icestorm)) (native-inputs `(("git" ,git) ; for determining its own version string ("yosys" ,yosys) ; for tests @@ -362,8 +360,7 @@ FOSS FPGA place and route tool.") (base32 "15n2gv2hd7h23cci95ij7yr71fkxppb209sfdsmmngh3fik09rpn")))) (build-system gnu-build-system) (native-inputs - `(("gperf" ,gperf) - ("pkg-config" ,pkg-config))) + (list gperf pkg-config)) (inputs `(("tcl" ,tcl) ("tk" ,tk) @@ -400,7 +397,7 @@ simulator trace files (@dfn{FST}).") (base32 "1kq11if64zj84gv4w1q7l16fp17xjxl2wv5hc9dibr1z3m1gy67l")))) (build-system python-build-system) (propagated-inputs - `(("python-colorama" ,python-colorama))) + (list python-colorama)) (home-page "https://m-labs.hk/gateware/migen/") (synopsis "Python toolbox for building complex digital hardware") (description @@ -452,16 +449,16 @@ a hardware description and verification language. ") (lambda _ (delete-file "autogen.sh")))))) (native-inputs - `(("automake" ,automake) - ("autoconf" ,autoconf) - ("flex" ,flex) - ("gettext" ,gnu-gettext) - ("libtool" ,libtool) - ("pkg-config" ,pkg-config) - ("which" ,which) - ("check" ,check))) ; for the tests + (list automake + autoconf + flex + gnu-gettext + libtool + pkg-config + which + check)) ; for the tests (inputs - `(("llvm" ,llvm-9))) + (list llvm-9)) (synopsis "VHDL compiler and simulator") (description "This package provides a VHDL compiler and simulator.") (home-page "https://github.com/nickg/nvc") @@ -479,7 +476,7 @@ a hardware description and verification language. ") "systemc/systemc-" version ".tar.gz")) (sha256 (base32 "0gvv3xmhiwx1izmzy06yslzqzh6ygrgmw53xqfmyvbz5a6ivk0ap")))) - (native-inputs `(("perl" ,perl))) + (native-inputs (list perl)) (build-system gnu-build-system) (arguments '(#:configure-flags '("--enable-debug"))) (home-page "https://accellera.org/community/systemc") @@ -518,8 +515,7 @@ using different abstraction levels.") ("gettext" ,gettext-minimal) ("python" ,python))) (inputs - `(("perl" ,perl) - ("systemc" ,systemc))) + (list perl systemc)) (build-system gnu-build-system) (arguments '(#:configure-flags |