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-rw-r--r--gnu/packages/fpga.scm7
1 files changed, 4 insertions, 3 deletions
diff --git a/gnu/packages/fpga.scm b/gnu/packages/fpga.scm
index f3dc805e36..60c5f96a87 100644
--- a/gnu/packages/fpga.scm
+++ b/gnu/packages/fpga.scm
@@ -1,6 +1,7 @@
 ;;; GNU Guix --- Functional package management for GNU
 ;;; Copyright © 2016 Danny Milosavljevic <dannym@scratchpost.org>
 ;;; Copyright © 2016, 2017 Theodoros Foradis <theodoros@foradis.org>
+;;; Copyright © 2018 Tobias Geerinckx-Rice <me@tobias.gr>
 ;;;
 ;;; This file is part of GNU Guix.
 ;;;
@@ -83,7 +84,7 @@ formal verification.")
 (define-public iverilog
   (package
     (name "iverilog")
-    (version "10.1.1")
+    (version "10.2")
     (source (origin
               (method url-fetch)
               (uri
@@ -91,7 +92,7 @@ formal verification.")
                               "verilog-" version ".tar.gz"))
               (sha256
                 (base32
-                   "1nnassxvq30rnn0r2p85rkb2zwxk97p109y13x3vr365wzgpbapx"))))
+                   "0075x5nsxwkrgn7b3635il9kw7mslckaji518pdmwdrdn7fxppln"))))
     (build-system gnu-build-system)
     (native-inputs
      `(("flex" ,flex)
@@ -104,7 +105,7 @@ It operates as a compiler, compiling source code written in Verilog
 (IEEE-1364) into some target format.
 For batch simulation, the compiler can generate an intermediate form
 called vvp assembly.
-This intermediate form is executed by the ``vvp'' command.
+This intermediate form is executed by @command{vvp}.
 For synthesis, the compiler generates netlists in the desired format.")
     ;; GPL2 only because of:
     ;; - ./driver/iverilog.man.in