diff options
Diffstat (limited to 'gnu/packages/patches/ath9k-htc-firmware-gcc.patch')
| -rw-r--r-- | gnu/packages/patches/ath9k-htc-firmware-gcc.patch | 119 |
1 files changed, 119 insertions, 0 deletions
diff --git a/gnu/packages/patches/ath9k-htc-firmware-gcc.patch b/gnu/packages/patches/ath9k-htc-firmware-gcc.patch new file mode 100644 index 0000000000..79924ca8cb --- /dev/null +++ b/gnu/packages/patches/ath9k-htc-firmware-gcc.patch @@ -0,0 +1,119 @@ +This GCC patch is from the ath9k-htc-firmware repository (version 1.3.2). +Not applying it (apparently) leads to miscompiled firmware, and loading it +fails with a "Target is unresponsive" message from the 'ath9k_htc' module. + +From c7162b8a3db42e7faf47606d3aa3dd61e64aea17 Mon Sep 17 00:00:00 2001 +From: Sujith Manoharan <c_manoha@qca.qualcomm.com> +Date: Mon, 7 Jan 2013 16:06:28 +0530 +Subject: [PATCH] gcc: AR9271/AR7010 config + +Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com> +--- + include/xtensa-config.h | 36 +++++++++++++++++------------------- + 1 file changed, 17 insertions(+), 19 deletions(-) + +diff --git a/include/xtensa-config.h b/include/xtensa-config.h +index 30f4f41..fe9b051 100644 +--- a/include/xtensa-config.h ++++ b/include/xtensa-config.h +@@ -1,7 +1,7 @@ + /* Xtensa configuration settings. +- Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2010 ++ Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007 + Free Software Foundation, Inc. +- Contributed by Bob Wilson (bob.wilson@acm.org) at Tensilica. ++ Contributed by Bob Wilson (bwilson@tensilica.com) at Tensilica. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by +@@ -44,10 +44,7 @@ + #define XCHAL_HAVE_L32R 1 + + #undef XSHAL_USE_ABSOLUTE_LITERALS +-#define XSHAL_USE_ABSOLUTE_LITERALS 0 +- +-#undef XSHAL_HAVE_TEXT_SECTION_LITERALS +-#define XSHAL_HAVE_TEXT_SECTION_LITERALS 1 /* Set if there is some memory that allows both code and literals. */ ++#define XSHAL_USE_ABSOLUTE_LITERALS 1 + + #undef XCHAL_HAVE_MAC16 + #define XCHAL_HAVE_MAC16 0 +@@ -59,10 +56,10 @@ + #define XCHAL_HAVE_MUL32 1 + + #undef XCHAL_HAVE_MUL32_HIGH +-#define XCHAL_HAVE_MUL32_HIGH 0 ++#define XCHAL_HAVE_MUL32_HIGH 1 + + #undef XCHAL_HAVE_DIV32 +-#define XCHAL_HAVE_DIV32 1 ++#define XCHAL_HAVE_DIV32 0 + + #undef XCHAL_HAVE_NSA + #define XCHAL_HAVE_NSA 1 +@@ -103,8 +100,6 @@ + #undef XCHAL_HAVE_FP_RSQRT + #define XCHAL_HAVE_FP_RSQRT 0 + +-#undef XCHAL_HAVE_DFP_accel +-#define XCHAL_HAVE_DFP_accel 0 + #undef XCHAL_HAVE_WINDOWED + #define XCHAL_HAVE_WINDOWED 1 + +@@ -119,32 +114,32 @@ + + + #undef XCHAL_ICACHE_SIZE +-#define XCHAL_ICACHE_SIZE 16384 ++#define XCHAL_ICACHE_SIZE 0 + + #undef XCHAL_DCACHE_SIZE +-#define XCHAL_DCACHE_SIZE 16384 ++#define XCHAL_DCACHE_SIZE 0 + + #undef XCHAL_ICACHE_LINESIZE +-#define XCHAL_ICACHE_LINESIZE 32 ++#define XCHAL_ICACHE_LINESIZE 16 + + #undef XCHAL_DCACHE_LINESIZE +-#define XCHAL_DCACHE_LINESIZE 32 ++#define XCHAL_DCACHE_LINESIZE 16 + + #undef XCHAL_ICACHE_LINEWIDTH +-#define XCHAL_ICACHE_LINEWIDTH 5 ++#define XCHAL_ICACHE_LINEWIDTH 4 + + #undef XCHAL_DCACHE_LINEWIDTH +-#define XCHAL_DCACHE_LINEWIDTH 5 ++#define XCHAL_DCACHE_LINEWIDTH 4 + + #undef XCHAL_DCACHE_IS_WRITEBACK +-#define XCHAL_DCACHE_IS_WRITEBACK 1 ++#define XCHAL_DCACHE_IS_WRITEBACK 0 + + + #undef XCHAL_HAVE_MMU + #define XCHAL_HAVE_MMU 1 + + #undef XCHAL_MMU_MIN_PTE_PAGE_SIZE +-#define XCHAL_MMU_MIN_PTE_PAGE_SIZE 12 ++#define XCHAL_MMU_MIN_PTE_PAGE_SIZE 29 + + + #undef XCHAL_HAVE_DEBUG +@@ -157,8 +152,11 @@ + #define XCHAL_NUM_DBREAK 2 + + #undef XCHAL_DEBUGLEVEL +-#define XCHAL_DEBUGLEVEL 6 ++#define XCHAL_DEBUGLEVEL 4 ++ + ++#undef XCHAL_EXCM_LEVEL ++#define XCHAL_EXCM_LEVEL 3 + + #undef XCHAL_MAX_INSTRUCTION_SIZE + #define XCHAL_MAX_INSTRUCTION_SIZE 3 +-- +1.8.1 + |