From 66b1471199cc077feb39ae58d5365e03f71f8fdb Mon Sep 17 00:00:00 2001
From: Cayetano Santos <csantosb@inventati.org>
Date: Sat, 9 Nov 2024 20:08:24 +0100
Subject: gnu: iverilog: Re-add zlib to inputs.

Fixes issue introduced in
<https://git.savannah.gnu.org/cgit/guix.git/commit/?id=b32f8bc9da> which
removed zlib.  This caused failures in the yosys test suite.

* gnu/packages/fpga.scm (iverilog) [inputs]: Add zlib.

Change-Id: I262db5db43527a3a2a1753163f7b9a4104f7e895
Signed-off-by: Maxim Cournoyer <maxim.cournoyer@gmail.com>
---
 gnu/packages/fpga.scm | 1 +
 1 file changed, 1 insertion(+)

(limited to 'gnu')

diff --git a/gnu/packages/fpga.scm b/gnu/packages/fpga.scm
index c658ed8da4..ecf111f8be 100644
--- a/gnu/packages/fpga.scm
+++ b/gnu/packages/fpga.scm
@@ -124,6 +124,7 @@ formal verification.")
       #:make-flags #~(list (string-append "PREFIX=" #$output))
       #:bootstrap-scripts #~(list "autoconf.sh")))
     (native-inputs (list autoconf bison flex gperf))
+    (inputs (list zlib))
     (home-page "https://steveicarus.github.io/iverilog")
     (synopsis "FPGA Verilog simulation and synthesis tool")
     (description
-- 
cgit 1.4.1