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| author | Quentin Carbonneaux <quentin.carbonneaux@yale.edu> | 2015-08-19 11:41:05 -0400 |
|---|---|---|
| committer | Quentin Carbonneaux <quentin.carbonneaux@yale.edu> | 2015-09-15 23:01:32 -0400 |
| commit | f48fc69f9eb49cdece7752545c76114eff065bef (patch) | |
| tree | 5c240025d2a96abac5564921c20b1888ad04e0ee | |
| parent | 95bcc46e151b224f51c9fc37175baa1537fe63d0 (diff) | |
| download | roux-f48fc69f9eb49cdece7752545c76114eff065bef.tar.gz | |
treat two instruction args uniformly in rega
| -rw-r--r-- | lisc/rega.c | 30 |
1 files changed, 14 insertions, 16 deletions
diff --git a/lisc/rega.c b/lisc/rega.c index 6b29546..585bb1e 100644 --- a/lisc/rega.c +++ b/lisc/rega.c @@ -351,22 +351,20 @@ rega(Fn *fn) i->to = reg(r, i->to.val); } else r = 0; - if (rtype(i->arg[0]) == RTmp) { - /* <arch> - * on Intel, we attempt to - * use the same register - * for the return and the - * first argument - */ - t = i->arg[0].val; - if (tmp[t].hint == -1 && r) - tmp[t].hint = r; - i->arg[0] = ralloc(&cur, t); - } - if (rtype(i->arg[1]) == RTmp) { - t = i->arg[1].val; - i->arg[1] = ralloc(&cur, t); - } + for (x=0; x<2; x++) + if (rtype(i->arg[x]) == RTmp) { + /* <arch> + * on Intel, we attempt to + * use the same register + * for the return and one + * argument + */ + t = i->arg[x].val; + if (r && !BGET(cur.b, r)) + if (tmp[t].hint == -1) + tmp[t].hint = r; + i->arg[x] = ralloc(&cur, t); + } } b->in = cur.b; for (p=b->phi; p; p=p->link) |