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| author | Quentin Carbonneaux <quentin@c9x.me> | 2022-08-31 17:09:04 +0200 |
|---|---|---|
| committer | Quentin Carbonneaux <quentin@c9x.me> | 2022-10-03 10:41:03 +0200 |
| commit | a9a70e30a8205a8f835c59fd8297e4a4483cc8d4 (patch) | |
| tree | a4551f26f719951a2301dc248168af385f4ebc68 /amd64/targ.c | |
| parent | 0b26cd4f5ecff8a01fb3f0adb902c14e043581e9 (diff) | |
| download | roux-a9a70e30a8205a8f835c59fd8297e4a4483cc8d4.tar.gz | |
add new target-specific abi0 pass
The general idea is to give abis a
chance to talk before we've done all
the optimizations. Currently, all
targets eliminate {par,arg,ret}{sb,ub,...}
during this pass. The forthcoming
arm64_apple will, however, insert
proper extensions during abi0.
Moving forward abis can, for example,
lower small-aggregates passing there
so that memory optimizations can
interact better with function calls.
Diffstat (limited to 'amd64/targ.c')
| -rw-r--r-- | amd64/targ.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/amd64/targ.c b/amd64/targ.c index e58ba2f..74fba4d 100644 --- a/amd64/targ.c +++ b/amd64/targ.c @@ -24,7 +24,8 @@ amd64_memargs(int op) .retregs = amd64_sysv_retregs, \ .argregs = amd64_sysv_argregs, \ .memargs = amd64_memargs, \ - .abi = amd64_sysv_abi, \ + .abi0 = elimsb, \ + .abi1 = amd64_sysv_abi, \ .isel = amd64_isel, \ Target T_amd64_sysv = { |