summary refs log tree commit diff
path: root/arm64/emit.c
diff options
context:
space:
mode:
authorMichael Forney <mforney@mforney.org>2020-04-19 16:31:55 -0700
committerQuentin Carbonneaux <quentin@c9x.me>2020-08-06 10:09:28 +0200
commit84f1e2950b3ab41523f25d205c99e9d8afd7ebba (patch)
tree1f5fa855fc58f26dd7ba75ea36dc3d157a4db606 /arm64/emit.c
parent706d6beca6218caf76f0107d15e79a8f3af1646a (diff)
downloadroux-84f1e2950b3ab41523f25d205c99e9d8afd7ebba.tar.gz
arm64: Make sure SP stays aligned by 16
According to the ARMv8 overview document

  However if SP is used as the base register then the value of the stack
  pointer prior to adding any offset must be quadword (16 byte) aligned,
  or else a stack alignment exception will be generated.

This manifests as a bus error on my system.

To resolve this, just save registers two at a time with stp.
Diffstat (limited to 'arm64/emit.c')
-rw-r--r--arm64/emit.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/arm64/emit.c b/arm64/emit.c
index 59e1aae..892d027 100644
--- a/arm64/emit.c
+++ b/arm64/emit.c
@@ -378,8 +378,8 @@ arm64_emitfn(Fn *fn, FILE *out)
 	if (e->fn->vararg) {
 		for (n=7; n>=0; n--)
 			fprintf(e->f, "\tstr\tq%d, [sp, -16]!\n", n);
-		for (n=7; n>=0; n--)
-			fprintf(e->f, "\tstr\tx%d, [sp, -8]!\n", n);
+		for (n=7; n>=0; n-=2)
+			fprintf(e->f, "\tstp\tx%d, x%d, [sp, -16]!\n", n-1, n);
 	}
 
 	if (e->frame + 16 <= 512)