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author | Quentin Carbonneaux <quentin.carbonneaux@yale.edu> | 2015-08-16 14:19:54 -0400 |
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committer | Quentin Carbonneaux <quentin.carbonneaux@yale.edu> | 2015-09-15 23:01:31 -0400 |
commit | 7bbd361083db3f08e173bbf384e7369ab5ffee57 (patch) | |
tree | ac03cab8b793006864c97dff7b0fbe91c0129f98 /lisc/emit.c | |
parent | 27f4eae43eebb4990bad59c8becdca41d2fb865d (diff) | |
download | roux-7bbd361083db3f08e173bbf384e7369ab5ffee57.tar.gz |
add the mul instruction
Diffstat (limited to 'lisc/emit.c')
-rw-r--r-- | lisc/emit.c | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/lisc/emit.c b/lisc/emit.c index 22e9073..2f96c3c 100644 --- a/lisc/emit.c +++ b/lisc/emit.c @@ -137,6 +137,7 @@ eins(Ins i, Fn *fn, FILE *f) static char *otoa[NOp] = { [OAdd] = "add", [OSub] = "sub", + [OMul] = "imul", [OAnd] = "and", [OLoad] = "mov", [OLoadss] = "movsw", @@ -154,10 +155,26 @@ eins(Ins i, Fn *fn, FILE *f) [OStores - OStorel] = "w", [OStoreb - OStorel] = "b", }; + Ref r0, r1; int reg; int64_t val; switch (i.op) { + case OMul: + if (rtype(i.arg[1]) == RCon) { + r0 = i.arg[1]; + r1 = i.arg[0]; + } else { + r0 = i.arg[0]; + r1 = i.arg[1]; + } + if (rtype(r0) == RCon && rtype(r1) == RTmp) { + val = fn->con[r0.val].val; + fprintf(f, "\timul $%"PRId64", %%%s, %%%s\n", + val, rtoa(r1.val), rtoa(i.to.val)); + break; + } + /* fall through */ case OAdd: case OSub: case OAnd: |