| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2022-05-10 | arm64: fix maximum immediate size for small loads/stores | Michael Forney | |
| The maximum immediate size for 1, 2, 4, and 8 byte loads/stores is 4095, 8190, 16380, and 32760 respectively[0][1][2]. [0] https://developer.arm.com/documentation/dui0802/a/A64-Data-Transfer-Instructions/LDRB--immediate- [1] https://developer.arm.com/documentation/dui0802/a/A64-Data-Transfer-Instructions/LDRH--immediate- [2] https://developer.arm.com/documentation/dui0802/a/A64-Data-Transfer-Instructions/LDR--immediate- | |||
| 2022-04-11 | move nx stack annotation to gas.c | Quentin Carbonneaux | |
| 2022-04-11 | Close input file after done reading | Daniel Xu | |
| Leaks resources to not close. Signed-off-by: Daniel Xu <dxu@dxuuu.xyz> | |||
| 2022-04-11 | do not leak type fields | Quentin Carbonneaux | |
| Thanks to Daniel Xu for reporting. | |||
| 2022-03-17 | amd64: restore previous name of amd64_sysv target | Michael Forney | |
| 2022-03-17 | fix return for big aggregates | Quentin Carbonneaux | |
| The recent changes in arm and riscv typclass() set ngp to 1 when a struct is returned via a caller-provided buffer. This interacts bogusly with selret() that ends up declaring a gp register live when none is set in the returning sequence. The fix is simply to set cty to zero (all registers dead) in case a caller- provided buffer is used. | |||
| 2022-03-15 | detect target in tests | Quentin Carbonneaux | |
| 2022-03-15 | new -t? flag to print default target | Quentin Carbonneaux | |
| 2022-03-15 | homogenize riscv and arm abis | Quentin Carbonneaux | |
| 2022-03-15 | support env calls on arm64 | Quentin Carbonneaux | |
| The x9 register is used for the env parameter. | |||
| 2022-03-15 | fix register count in riscv argregs | Quentin Carbonneaux | |
| 2022-03-14 | dynamic stack allocs for arm64 | Quentin Carbonneaux | |
| I also moved some isel logic that would have been repeated a third time in util.c. | |||
| 2022-03-14 | add rv64/ to README | Quentin Carbonneaux | |
| 2022-03-14 | output symbol type and size | Quentin Carbonneaux | |
| That is not available on osx so I tweaked the gas.c api a little to conditionally output the two directives. | |||
| 2022-03-14 | improve consistency in abis | Quentin Carbonneaux | |
| 2022-03-14 | arm64/abi: fix big aggregates passed on the stack | Quentin Carbonneaux | |
| The riscv test abi8.ssa caught a bug in the arm backend. It turns out we were using the wrong class when loading pointers to aggregates from the stack. The fix is simple and mirrors what is done in the riscv abi. | |||
| 2022-03-11 | dust off antique .tag | Quentin Carbonneaux | |
| 2022-03-10 | rv64: plug holes in the abi | Quentin Carbonneaux | |
| Many things got fixed, but the most notable change is the proper support of floating point types in aggregates. Minor fixes: - selpar() did not deal correctly with Cfpint - typclass() was reading out of bounds in the gp/fp arrays - support for env calls | |||
| 2022-03-10 | two new tests in abi5.ssa | Quentin Carbonneaux | |
| They are meant to exercise the hardware floating-point calling convention of the risc-v target. | |||
| 2022-03-10 | new abi stress test | Quentin Carbonneaux | |
| 2022-03-08 | flag types defined as unions | Quentin Carbonneaux | |
| The risc-v abi needs to know if a type is defined as a union or not. We cannot use nunion to obtain this information because the risc-v abi made the unfortunate decision of treating union { int i; } differently from int i; So, instead, I introduce a single bit flag 'isunion'. | |||
| 2022-03-08 | cosmetics | Quentin Carbonneaux | |
| 2022-03-07 | doc: export function main in hello world example | lincoln auster [they/them] | |
| This enables the example to be compiled and run as-is, without any additional modification. | |||
| 2022-02-27 | rv64: formatting and bug fix in epilogue | Quentin Carbonneaux | |
| 2022-02-27 | doc: Add missing neg entry to index | Scott Graham | |
| 2022-02-27 | rv64: cosmetics in isel | Quentin Carbonneaux | |
| 2022-02-25 | disable pie for rv64 tests | Quentin Carbonneaux | |
| 2022-02-25 | improve consistency in arm64 and rv64 abis | Quentin Carbonneaux | |
| 2022-02-24 | parse: allow string after first data item | Paul Ouellette | |
| 2022-02-24 | doc: minor fixes | Paul Ouellette | |
| 2022-02-24 | fix folding of shifts of word operand by >32 | Paul Ouellette | |
| 2022-02-17 | add rv64 backend | Michael Forney | |
| It is mostly complete, but still has a few ABI bugs when passing floats in structs, or when structs are passed partly in register, and partly on stack. | |||
| 2022-02-17 | test: add c[u]od checks to isel2 and add new integer compare test isel3 | Michael Forney | |
| 2022-02-17 | cfg: remove unnecessary check for jump type | Michael Forney | |
| This condition should match any jump with two successors. This is needed on riscv64, where there is no flags register, so Jjnz is used all the way to emit(). | |||
| 2022-02-17 | Revert "skip jump arguments in rega" | Michael Forney | |
| This reverts commit 028534d9897079bf64559dca0402bc59a956ce46. riscv64 will have jump arguments with type RTmp. | |||
| 2022-02-17 | spill: consider jump argument as use of register | Michael Forney | |
| 2022-02-11 | document the automatic use of bss | Quentin Carbonneaux | |
| 2022-02-11 | gas: put zero data into .bss by default | Michael Forney | |
| This allows frontends to use BSS generically, without knowledge of platform-dependent details. | |||
| 2022-02-11 | doc: fix name of export linkage flag | Paul Ouellette | |
| 2022-02-02 | shared linkage logic for func/data | Quentin Carbonneaux | |
| 2022-01-31 | arm64: handle large slots in Ocopy | Quentin Carbonneaux | |
| 2022-01-31 | Do not use the asm keyword as a local variable | Detlef Riekenberg | |
| Signed-off-by: Detlef Riekenberg <wine.dev@web.de> | |||
| 2022-01-28 | amd64/isel: nits | Quentin Carbonneaux | |
| 2022-01-28 | fix test/fpcnv (wrong spacing) | Quentin Carbonneaux | |
| 2022-01-28 | update token hash params | Quentin Carbonneaux | |
| 2022-01-28 | implement float -> unsigned casts | Bor Grošelj Simić | |
| amd64 lacks instruction for this so it has to be implemented with float -> signed casts. The approach is borrowed from llvm. | |||
| 2022-01-28 | implement unsigned -> float casts | Bor Grošelj Simić | |
| amd64 lacks an instruction for this so it has to be implemented with signed -> float casts: - Word casting is done by zero-extending the word to a long and then doing a regular signed cast. - Long casting is done by dividing by two with correct rounding if the highest bit is set and casting that to float, then adding 1 to mantissa with integer addition | |||
| 2022-01-23 | increase token limit to 255 | Bor Grošelj Simić | |
| 2022-01-23 | bump copyright year | Quentin Carbonneaux | |
| 2022-01-23 | check for fopen() errors for output file | Bor Grošelj Simić | |
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index : ~cnx/roux | |
| Alternative QBE compiler |
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