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2015-09-15add crippled dce to the allocatorQuentin Carbonneaux
2015-09-15complete a crude register allocatorQuentin Carbonneaux
2015-09-15start work on parallel movesQuentin Carbonneaux
2015-09-15initiate work on reg allocationQuentin Carbonneaux
2015-09-15simplify spillerQuentin Carbonneaux
It seems that this logic of shuffling stuff around between blocks should be handled by the register allocator instead: it *will* have to shuffle between registers, so we might as well mix some spill locations in.
2015-09-15finish spiller, now needs testing!Quentin Carbonneaux
2015-09-15new euclidean division testQuentin Carbonneaux
2015-09-15add more printing supportQuentin Carbonneaux
2015-09-15standardize error messageQuentin Carbonneaux
2015-09-15factor some spilling logicQuentin Carbonneaux
2015-09-15comment and fix if(BSET(..)) bugQuentin Carbonneaux
2015-09-15new spill testQuentin Carbonneaux
2015-09-15test iselQuentin Carbonneaux
2015-09-15isel logic was moved to spillQuentin Carbonneaux
2015-09-15add slot addressing and some more spillingQuentin Carbonneaux
2015-09-15add simple spill testQuentin Carbonneaux
2015-09-15prepare for block processingQuentin Carbonneaux
2015-09-15this makefile fu was uselessQuentin Carbonneaux
2015-09-15always preserve last buildQuentin Carbonneaux
2015-09-15refine assertion in cost computationQuentin Carbonneaux
2015-09-15rework spilling code for jump argumentsQuentin Carbonneaux
2015-09-15refine precision of loop use setsQuentin Carbonneaux
2015-09-15move some debug output out of mainQuentin Carbonneaux
2015-09-15simplify tests for hdQuentin Carbonneaux
2015-09-15nicer debug, bug fixed in loop detectionQuentin Carbonneaux
2015-09-15cosmeticsQuentin Carbonneaux
2015-09-15alt.ssa was in buggy ssa formQuentin Carbonneaux
2015-09-15attempt to fix loop uses/pressure in spillQuentin Carbonneaux
2015-09-15improve output, add debug arrayQuentin Carbonneaux
2015-09-15correct phi usage accountingQuentin Carbonneaux
2015-09-15show more spilling dataQuentin Carbonneaux
2015-09-15simplificationsQuentin Carbonneaux
2015-09-15attempt more correct loop markingQuentin Carbonneaux
2015-09-15add a live-through temporary to test altQuentin Carbonneaux
2015-09-15more testing codeQuentin Carbonneaux
2015-09-15test code for the spillerQuentin Carbonneaux
2015-09-15cosmeticsQuentin Carbonneaux
2015-09-15start working with loops in spill.cQuentin Carbonneaux
2015-09-15rework liveness to compute reg pressureQuentin Carbonneaux
2015-09-15add pressure in left block of alt.ssaQuentin Carbonneaux
2015-09-15add fun example!Quentin Carbonneaux
2015-09-15fix some instruction emitting codeQuentin Carbonneaux
2015-09-15start work on spillerQuentin Carbonneaux
2015-09-15define curi as a global tooQuentin Carbonneaux
2015-09-15single bit bitfield needs to be unsignedQuentin Carbonneaux
2015-09-15fix small type issuesQuentin Carbonneaux
2015-09-15start simple work on iselQuentin Carbonneaux
2015-09-15export error functionsQuentin Carbonneaux
2015-09-15rename mod to remQuentin Carbonneaux
2015-09-15remove useless typedefsQuentin Carbonneaux