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The recent changes in arm and riscv
typclass() set ngp to 1 when a struct
is returned via a caller-provided
buffer. This interacts bogusly with
selret() that ends up declaring a gp
register live when none is set in
the returning sequence.
The fix is simply to set cty to zero
(all registers dead) in case a caller-
provided buffer is used.
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The x9 register is used for
the env parameter.
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I also moved some isel logic
that would have been repeated
a third time in util.c.
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That is not available on osx
so I tweaked the gas.c api
a little to conditionally
output the two directives.
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The riscv test abi8.ssa caught a bug
in the arm backend. It turns out we
were using the wrong class when loading
pointers to aggregates from the stack.
The fix is simple and mirrors what is
done in the riscv abi.
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Many things got fixed, but the most
notable change is the proper support
of floating point types in aggregates.
Minor fixes:
- selpar() did not deal correctly
with Cfpint
- typclass() was reading out of
bounds in the gp/fp arrays
- support for env calls
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They are meant to exercise the
hardware floating-point calling
convention of the risc-v target.
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The risc-v abi needs to know if a
type is defined as a union or not.
We cannot use nunion to obtain this
information because the risc-v abi
made the unfortunate decision of
treating
union { int i; }
differently from
int i;
So, instead, I introduce a single
bit flag 'isunion'.
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This enables the example to be compiled and run as-is, without any
additional modification.
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It is mostly complete, but still has a few ABI bugs when passing
floats in structs, or when structs are passed partly in register,
and partly on stack.
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This condition should match any jump with two successors. This is
needed on riscv64, where there is no flags register, so Jjnz is
used all the way to emit().
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This reverts commit 028534d9897079bf64559dca0402bc59a956ce46.
riscv64 will have jump arguments with type RTmp.
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This allows frontends to use BSS generically, without knowledge of
platform-dependent details.
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Signed-off-by: Detlef Riekenberg <wine.dev@web.de>
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amd64 lacks instruction for this so it has to be implemented with
float -> signed casts. The approach is borrowed from llvm.
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amd64 lacks an instruction for this so it has to be implemented with
signed -> float casts:
- Word casting is done by zero-extending the word to a long and then doing
a regular signed cast.
- Long casting is done by dividing by two with correct rounding if the
highest bit is set and casting that to float, then adding
1 to mantissa with integer addition
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Necessary for floating-point negation, because
`%result = sub 0, %operand` doesn't give the correct sign for 0/-0.
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When slots are used with a large offset,
the emitter generates invalid assembly
code. That is caught later on by the
assembler, but it prevents compilation
of programs with large stack frames.
When a slot offset is too large to be
expressed as a constant offset to x29
(the frame pointer), emitins() inserts
a late Oaddr instruction to x16 and
replaces the large slot reference with
x16.
This change also gave me the opportunity
to refactor the save/restore logic for
callee-save registers.
This fixes the following Hare issue:
https://todo.sr.ht/~sircmpwn/hare/387
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parseref() has code to reuse address constants, but this is not
done in other passes such as fold or isel. Introduce a new function
newcon() which takes a Con and returns a Ref for that constant, and
use this whenever creating address constants.
This is necessary to fix folding of address constants when one
operand is already folded. For example, in
%a =l add $x, 1
%b =l add %a, 2
%c =w loadw %b
%a and %b were folded to $x+1 and $x+3 respectively, but then the
second add is visited again since it uses %a. This gets folded to
$x+3 as well, but as a new distinct constant. This results in %b
getting labeled as bottom instead of either constant, disabling the
replacement of %b by a constant in subsequent instructions (such
as the loadw).
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