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2015-09-15use regs of the correct type in iselQuentin Carbonneaux
2015-09-15use a new Ref type for registersQuentin Carbonneaux
This might not be a good idea, the problem was that many spurious registers would be added to the Bits data-structures during compilation (and would always remain 0). However, doing the above modification de-uniformizes the handling of temps and regs, this makes the code longer and not really nicer. Also, additional Bits structures are required to track the registers independently. Overall this might be a bad idea to revert.
2015-09-15patch isel to use symbol typesQuentin Carbonneaux
2015-09-15silence clang warningQuentin Carbonneaux
2015-09-15avoid name conflicts in enumsQuentin Carbonneaux
2015-09-15start change of representation for registersQuentin Carbonneaux
2015-09-15start work on word/long handlingQuentin Carbonneaux
2015-09-15replace IA with X for x64 instructionsQuentin Carbonneaux
2015-09-15avoid keyword clash by using cons for constantsQuentin Carbonneaux
2015-09-15cosmetic modifications to parse.cQuentin Carbonneaux
2015-09-15clean the commutativity + fix bug in emitQuentin Carbonneaux
The commutativity information only makes sense for arithmetic expressions. To account for that, I introduced a new tri-valued boolean type B3. Memory operations, for example, will receive an undefined commutativity trit. The code emitter was buggy when rega emitted instructions like 'rax = add 1, rax', this is now fixed using the commutativity information (we rewrite it in 'rax = add rax, 1').
2015-09-15cosmeticsQuentin Carbonneaux
2015-09-15compress parsref code a littleQuentin Carbonneaux
2015-09-15start improving constants supportQuentin Carbonneaux
2015-09-15add TODOQuentin Carbonneaux
2015-09-15add support for in-block reg. contraintsQuentin Carbonneaux
2015-09-15perform isel before code emissionQuentin Carbonneaux
2015-09-15emit some x86-sepcific instructionsQuentin Carbonneaux
2015-09-15compile emit moduleQuentin Carbonneaux
2015-09-15add a code emitter for at&t syntaxQuentin Carbonneaux
2015-09-15silence clang warningQuentin Carbonneaux
2015-09-15add crippled dce to the allocatorQuentin Carbonneaux
2015-09-15complete a crude register allocatorQuentin Carbonneaux
2015-09-15start work on parallel movesQuentin Carbonneaux
2015-09-15initiate work on reg allocationQuentin Carbonneaux
2015-09-15simplify spillerQuentin Carbonneaux
It seems that this logic of shuffling stuff around between blocks should be handled by the register allocator instead: it *will* have to shuffle between registers, so we might as well mix some spill locations in.
2015-09-15finish spiller, now needs testing!Quentin Carbonneaux
2015-09-15new euclidean division testQuentin Carbonneaux
2015-09-15add more printing supportQuentin Carbonneaux
2015-09-15standardize error messageQuentin Carbonneaux
2015-09-15factor some spilling logicQuentin Carbonneaux
2015-09-15comment and fix if(BSET(..)) bugQuentin Carbonneaux
2015-09-15new spill testQuentin Carbonneaux
2015-09-15test iselQuentin Carbonneaux
2015-09-15isel logic was moved to spillQuentin Carbonneaux
2015-09-15add slot addressing and some more spillingQuentin Carbonneaux
2015-09-15add simple spill testQuentin Carbonneaux
2015-09-15prepare for block processingQuentin Carbonneaux
2015-09-15this makefile fu was uselessQuentin Carbonneaux
2015-09-15always preserve last buildQuentin Carbonneaux
2015-09-15refine assertion in cost computationQuentin Carbonneaux
2015-09-15rework spilling code for jump argumentsQuentin Carbonneaux
2015-09-15refine precision of loop use setsQuentin Carbonneaux
2015-09-15move some debug output out of mainQuentin Carbonneaux
2015-09-15simplify tests for hdQuentin Carbonneaux
2015-09-15nicer debug, bug fixed in loop detectionQuentin Carbonneaux
2015-09-15cosmeticsQuentin Carbonneaux
2015-09-15alt.ssa was in buggy ssa formQuentin Carbonneaux
2015-09-15attempt to fix loop uses/pressure in spillQuentin Carbonneaux
2015-09-15improve output, add debug arrayQuentin Carbonneaux