From 49a4593c335126ba279f47328824abfef379725e Mon Sep 17 00:00:00 2001 From: Quentin Carbonneaux Date: Sat, 8 Apr 2017 21:06:33 -0400 Subject: prepare for multi-target This big diff does multiple changes to allow the addition of new targets to qbe. The changes are listed below in decreasing order of impact. 1. Add a new Target structure. To add support for a given target, one has to implement all the members of the Target structure. All the source files where changed to use this interface where needed. 2. Single out amd64-specific code. In this commit, the amd64 target T_amd64_sysv is the only target available, it is implemented in the amd64/ directory. All the non-static items in this directory are prefixed with either amd64_ or amd64_sysv (for items that are specific to the System V ABI). 3. Centralize Ops information. There is now a file 'ops.h' that must be used to store all the available operations together with their metadata. The various targets will only select what they need; but it is beneficial that there is only *one* place to change to add a new instruction. One good side effect of this change is that any operation 'xyz' in the IL now as a corresponding 'Oxyz' in the code. 4. Misc fixes. One notable change is that instruction selection now generates generic comparison operations and the lowering to the target's comparisons is done in the emitter. GAS directives for data are the same for many targets, so data emission was extracted in a file 'gas.c'. 5. Modularize the Makefile. The Makefile now has a list of C files that are target-independent (SRC), and one list of C files per target. Each target can also use its own 'all.h' header (for example to define registers). --- rega.c | 38 ++++++++++++++++++++------------------ 1 file changed, 20 insertions(+), 18 deletions(-) (limited to 'rega.c') diff --git a/rega.c b/rega.c index 3d83327..02429a6 100644 --- a/rega.c +++ b/rega.c @@ -8,8 +8,8 @@ typedef struct RMap RMap; struct RMap { - int t[NIReg+NFReg]; - int r[NIReg+NFReg]; + int t[Tmp0]; + int r[Tmp0]; BSet b[1]; int n; }; @@ -78,10 +78,12 @@ static void radd(RMap *m, int t, int r) { assert((t >= Tmp0 || t == r) && "invalid temporary"); - assert(((RAX <= r && r < RAX + NIReg) || (XMM0 <= r && r < XMM0 + NFReg)) && "invalid register"); + assert(((T.gpr0 <= r && r < T.gpr0 + T.ngpr) + || (T.fpr0 <= r && r < T.fpr0 + T.nfpr)) + && "invalid register"); assert(!bshas(m->b, t) && "temporary has mapping"); assert(!bshas(m->b, r) && "register already allocated"); - assert(m->n <= NIReg+NFReg && "too many mappings"); + assert(m->n <= T.ngpr+T.nfpr && "too many mappings"); bsset(m->b, t); bsset(m->b, r); m->t[m->n] = t; @@ -110,11 +112,11 @@ ralloc(RMap *m, int t) regs = tmp[phicls(t, tmp)].hint.m; regs |= m->b->t[0]; if (KBASE(tmp[t].cls) == 0) { - r0 = RAX; - r1 = RAX + NIReg; + r0 = T.gpr0; + r1 = r0 + T.ngpr; } else { - r0 = XMM0; - r1 = XMM0 + NFReg; + r0 = T.fpr0; + r1 = r0 + T.nfpr; } for (r=r0; r= Tmp0 || !(BIT(t) & RGLOB)); + assert(t >= Tmp0 || !(BIT(t) & T.rglob)); if (!bshas(m->b, t)) return -1; for (i=0; m->t[i] != t; i++) @@ -295,10 +297,10 @@ dopm(Blk *b, Ins *i, RMap *m) } while (i != b->ins && regcpy(i-1)); assert(m0.n <= m->n); if (i != b->ins && (i-1)->op == Ocall) { - def = retregs((i-1)->arg[1], 0); - for (r=0; rarg[1], 0) | T.rglob; + for (r=0; T.rsave[r]>=0; r++) + if (!(BIT(T.rsave[r]) & def)) + move(T.rsave[r], R, m); } for (npm=0, n=0; nn; n++) { t = m->t[n]; @@ -370,10 +372,10 @@ doblk(Blk *b, RMap *cur) for (i=&b->ins[b->nins]; i!=b->ins;) { switch ((--i)->op) { case Ocall: - rs = argregs(i->arg[1], 0); - for (r=0; rarg[1], 0) | T.rglob; + for (r=0; T.rsave[r]>=0; r++) + if (!(BIT(T.rsave[r]) & rs)) + rfree(cur, T.rsave[r]); break; case Ocopy: if (isreg(i->arg[0])) { @@ -388,7 +390,7 @@ doblk(Blk *b, RMap *cur) if (!req(i->to, R)) { assert(rtype(i->to) == RTmp); r = i->to.val; - if (r >= Tmp0 || !(BIT(r) & RGLOB)) + if (r >= Tmp0 || !(BIT(r) & T.rglob)) r = rfree(cur, r); if (r == -1) { assert(!isreg(i->to)); -- cgit 1.4.1