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| author | Simon South <simon@simonsouth.net> | 2023-02-10 08:16:54 -0500 |
|---|---|---|
| committer | Christopher Baines <mail@cbaines.net> | 2023-02-11 20:34:22 +0000 |
| commit | ade3bfd0361bfd62ef8faef6eb1ae9f776f6148b (patch) | |
| tree | 470d214a16c9cc13c8ca1abed6cec4d59762db4e | |
| parent | 9b1d051e6f62a10539b893f44746124edd708ee0 (diff) | |
| download | guix-ade3bfd0361bfd62ef8faef6eb1ae9f776f6148b.tar.gz | |
gnu: yosys: Do not propagate any inputs.
* gnu/packages/fpga.scm (yosys)[arguments]<#:phases>: Patch reference to z3 in "fix-paths" phase; in "use-external-abc" phase, use complete path to "abc" executable in store. [propagated-inputs]: Remove, moving abc and z3 from here... [inputs]: ...to here. Signed-off-by: Christopher Baines <mail@cbaines.net>
| -rw-r--r-- | gnu/packages/fpga.scm | 18 |
1 files changed, 11 insertions, 7 deletions
diff --git a/gnu/packages/fpga.scm b/gnu/packages/fpga.scm index 7b3c522bf7..4a01714e81 100644 --- a/gnu/packages/fpga.scm +++ b/gnu/packages/fpga.scm @@ -159,6 +159,9 @@ For synthesis, the compiler generates netlists in the desired format.") #~(modify-phases %standard-phases (add-before 'configure 'fix-paths (lambda* (#:key inputs #:allow-other-keys) + (substitute* "./backends/smt2/smtio.py" + (("\\['z3") + (string-append "['" (search-input-file inputs "/bin/z3")))) (substitute* "./passes/cmds/show.cc" (("exec xdot") (string-append "exec " (search-input-file inputs @@ -171,9 +174,11 @@ For synthesis, the compiler generates netlists in the desired format.") (lambda* (#:key make-flags #:allow-other-keys) (apply invoke "make" "config-gcc" make-flags))) (add-after 'configure 'use-external-abc - (lambda _ + (lambda* (#:key inputs #:allow-other-keys) (substitute* '("./Makefile") - (("ABCEXTERNAL \\?=") "ABCEXTERNAL = abc")))) + (("ABCEXTERNAL \\?=") + (string-append "ABCEXTERNAL = " + (search-input-file inputs "/bin/abc")))))) (add-before 'check 'fix-iverilog-references (lambda* (#:key inputs native-inputs #:allow-other-keys) (let ((iverilog (search-input-file (or native-inputs inputs) @@ -211,15 +216,14 @@ For synthesis, the compiler generates netlists in the desired format.") python tcl)) ; tclsh for the tests (inputs - (list graphviz + (list abc + graphviz libffi psmisc readline tcl - xdot)) - (propagated-inputs - (list abc - z3)) ; should be in path for yosys-smtbmc + xdot + z3)) (home-page "https://yosyshq.net/yosys/") (synopsis "FPGA Verilog RTL synthesizer") (description "Yosys synthesizes Verilog-2005.") |