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| author | Quentin Carbonneaux <quentin.carbonneaux@yale.edu> | 2015-10-24 20:53:29 -0400 |
|---|---|---|
| committer | Quentin Carbonneaux <quentin.carbonneaux@yale.edu> | 2015-10-30 13:20:42 -0400 |
| commit | d1f048bc9c8eacc5fb34ce39346de8f5388a201b (patch) | |
| tree | 7e7c75cb8ddc92486c49860f4830b19aa553e794 | |
| parent | 47a34dbd510ff890c4016d12ec8fbeaf5ae6e9c3 (diff) | |
| download | roux-d1f048bc9c8eacc5fb34ce39346de8f5388a201b.tar.gz | |
don't share mems containing temporaries
This can cause trouble in register allocation when these temporaries get replaced by registers. On the other hand, offsetted slots and constants can safely be shared.
| -rw-r--r-- | lisc/isel.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/lisc/isel.c b/lisc/isel.c index 1560d6d..6dc28ea 100644 --- a/lisc/isel.c +++ b/lisc/isel.c @@ -141,7 +141,9 @@ sel(Ins i, ANum *an, Fn *fn) vgrow(&fn->mem, ++fn->nmem); fn->mem[fn->nmem-1] = a; i.arg[0] = MEM(fn->nmem-1); - an[r0.val].mem = i.arg[0]; + if (rtype(a.base) != RTmp) + if (req(a.index, R)) + an[r0.val].mem = i.arg[0]; } else i.arg[0] = r1; } |