fix hinting bug in spiller

We have to first free the output register of an instruction
before setting the interference hints for inregs temporaries.

1 files changed, 3 insertions, 3 deletions

diff --git a/lisc/spill.c b/lisc/spill.c
index aaec562..ea89fd9 100644
--- a/lisc/spill.c
+++ b/lisc/spill.c
@@ -478,9 +478,6 @@ spill(Fn *fn)
 						i->arg[n] = slot(t);
 					}
 				}
-			r = v.t[0] & (BIT(Tmp0)-1);
-			if (r)
-				sethint(&v, r);
 			reloads(&u, &v);
 			if (!req(i->to, R)) {
 				t = i->to.val;
@@ -488,6 +485,9 @@ spill(Fn *fn)
 				BCLR(v, t);
 			}
 			emiti(*i);
+			r = v.t[0] & (BIT(Tmp0)-1);
+			if (r)
+				sethint(&v, r);
 		}
 		assert(!r || b==fn->start);