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| author | Quentin Carbonneaux <quentin.carbonneaux@yale.edu> | 2016-03-22 11:53:57 -0400 |
|---|---|---|
| committer | Quentin Carbonneaux <quentin.carbonneaux@yale.edu> | 2016-03-22 11:53:57 -0400 |
| commit | 337b10f6edc4d56cbf126255b3e63e6e0b7c8530 (patch) | |
| tree | da84c497678c8453bfa4d127c26aa8496b974947 /lisc/test/abi4.ssa | |
| parent | 5ad3eaa75a19db2c38406b9be693d60f624cb305 (diff) | |
| download | roux-337b10f6edc4d56cbf126255b3e63e6e0b7c8530.tar.gz | |
store register usage of ret instructions (abi fuzz)
So far I was ignoring register uses of return instructions
and it was working because at most one register could be
returned. Now that more complex returns are supported it
is necessary to keep track of the registers used by
returns.
The abi fuzzer triggered an assertion failure in the
register allocator with the following IL:
R1 =l load [%t16]
R3 =l load [8 + %t16]
ret
The regalloc would use R1 for %t16, and then a (nice)
assertion realized the inconsistent state because R1
could only be def'd by an assignment to %t16.
Diffstat (limited to 'lisc/test/abi4.ssa')
0 files changed, 0 insertions, 0 deletions