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authorQuentin Carbonneaux <quentin.carbonneaux@yale.edu>2016-12-28 06:43:05 -0500
committerQuentin Carbonneaux <quentin.carbonneaux@yale.edu>2016-12-28 06:43:05 -0500
commit52cc53185e44a7e8690fb5ec856863a4d259034b (patch)
treeeeccd9f316816b9af95211fb8c3c9344d1278473 /load.c
parent3c3afdc896be4de996d7486e40e7b81488b745b9 (diff)
downloadroux-52cc53185e44a7e8690fb5ec856863a4d259034b.tar.gz
loosen assertion in load elimination
The assertion was invalid, I was assuming il->blk was
b when writing it.  The new assertion should be right:
If the loop level were to decrease we would get out of
a cycle in cfg, this should not be possible unless we
go through a block with more than 1 predecessor.
Diffstat (limited to 'load.c')
-rw-r--r--load.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/load.c b/load.c
index 26bc2ca..56204dc 100644
--- a/load.c
+++ b/load.c
@@ -260,7 +260,7 @@ def(Slice sl, bits msk, Blk *b, Ins *i, Loc *il)
 		goto Load;
 	if (b->npred == 1) {
 		bp = b->pred[0];
-		assert(bp->s2 || bp->loop == il->blk->loop);
+		assert(bp->loop >= il->blk->loop);
 		l = *il;
 		if (bp->s2)
 			l.type = LNoLoad;