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author | Quentin Carbonneaux <quentin@c9x.me> | 2021-10-18 21:04:10 +0200 |
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committer | Quentin Carbonneaux <quentin@c9x.me> | 2021-10-22 23:53:25 +0200 |
commit | fcdef10dae54d7124aca9ccbefe53baa8e67267d (patch) | |
tree | 1215b60f1f3a31d38ee37228dd37bcc4a6a61f99 /load.c | |
parent | 9858a12730717d9c5e5deec4264d7041d75fc947 (diff) | |
download | roux-fcdef10dae54d7124aca9ccbefe53baa8e67267d.tar.gz |
make variadic args explicit
Some abis, like the riscv one, treat arguments differently depending on whether they are variadic or not. To prepare for the upcomming riscv target, we change the variadic call syntax and give meaning to the location of the '...' marker. # new syntax %ret =w call $f(w %regular, ..., w %variadic) By nature of their abis, the change is backwards compatible for existing targets.
Diffstat (limited to 'load.c')
-rw-r--r-- | load.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/load.c b/load.c index f3a695b..5d61a6c 100644 --- a/load.c +++ b/load.c @@ -234,7 +234,7 @@ def(Slice sl, bits msk, Blk *b, Ins *i, Loc *il) while (i > b->ins) { --i; if (killsl(i->to, sl) - || (iscall(i->op) && escapes(sl.ref, curf))) + || (i->op == Ocall && escapes(sl.ref, curf))) goto Load; ld = isload(i->op); if (ld) { |