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| author | Quentin Carbonneaux <quentin.carbonneaux@yale.edu> | 2016-12-28 06:43:05 -0500 |
|---|---|---|
| committer | Quentin Carbonneaux <quentin.carbonneaux@yale.edu> | 2016-12-28 06:43:05 -0500 |
| commit | 52cc53185e44a7e8690fb5ec856863a4d259034b (patch) | |
| tree | eeccd9f316816b9af95211fb8c3c9344d1278473 /tools | |
| parent | 3c3afdc896be4de996d7486e40e7b81488b745b9 (diff) | |
| download | roux-52cc53185e44a7e8690fb5ec856863a4d259034b.tar.gz | |
loosen assertion in load elimination
The assertion was invalid, I was assuming il->blk was b when writing it. The new assertion should be right: If the loop level were to decrease we would get out of a cycle in cfg, this should not be possible unless we go through a block with more than 1 predecessor.
Diffstat (limited to 'tools')
0 files changed, 0 insertions, 0 deletions