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author | Quentin Carbonneaux <quentin@c9x.me> | 2022-08-29 18:45:52 +0200 |
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committer | Quentin Carbonneaux <quentin@c9x.me> | 2022-08-31 21:42:49 +0200 |
commit | 8dddb971d923fa19dced39013e6d4a39676e065a (patch) | |
tree | 88192ecf3a60de73f06d03dab51dc51f17fb4ab7 /amd64/targ.c | |
parent | 5490268683c82ad07eac6d2e8296a45702a8381e (diff) | |
download | roux-8dddb971d923fa19dced39013e6d4a39676e065a.tar.gz |
drop -G flag and add target amd64_apple
apple support is more than assembly syntax in case of arm64 machines, and apple syntax is currently useless in all cases but amd64; rather than having a -G option that only makes sense with amd64, we add a new target amd64_apple
Diffstat (limited to 'amd64/targ.c')
-rw-r--r-- | amd64/targ.c | 42 |
1 files changed, 28 insertions, 14 deletions
diff --git a/amd64/targ.c b/amd64/targ.c index 2cf1bdc..e58ba2f 100644 --- a/amd64/targ.c +++ b/amd64/targ.c @@ -12,20 +12,34 @@ amd64_memargs(int op) return amd64_op[op].nmem; } +#define AMD64_COMMON \ + .gpr0 = RAX, \ + .ngpr = NGPR, \ + .fpr0 = XMM0, \ + .nfpr = NFPR, \ + .rglob = BIT(RBP) | BIT(RSP), \ + .nrglob = 2, \ + .rsave = amd64_sysv_rsave, \ + .nrsave = {NGPS, NFPS}, \ + .retregs = amd64_sysv_retregs, \ + .argregs = amd64_sysv_argregs, \ + .memargs = amd64_memargs, \ + .abi = amd64_sysv_abi, \ + .isel = amd64_isel, \ + Target T_amd64_sysv = { .name = "amd64_sysv", - .gpr0 = RAX, - .ngpr = NGPR, - .fpr0 = XMM0, - .nfpr = NFPR, - .rglob = BIT(RBP) | BIT(RSP), - .nrglob = 2, - .rsave = amd64_sysv_rsave, - .nrsave = {NGPS, NFPS}, - .retregs = amd64_sysv_retregs, - .argregs = amd64_sysv_argregs, - .memargs = amd64_memargs, - .abi = amd64_sysv_abi, - .isel = amd64_isel, - .emitfn = amd64_emitfn, + .emitfn = amd64_sysv_emitfn, + .emitfin = elf_emitfin, + .asloc = ".L", + AMD64_COMMON +}; + +Target T_amd64_apple = { + .name = "amd64_apple", + .emitfn = amd64_apple_emitfn, + .emitfin = macho_emitfin, + .asloc = "L", + .assym = "_", + AMD64_COMMON }; |